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TSA1401
14-BIT, 20MSPS, 85mW A/D CONVERTER
FEATURES
s OPTIMWATTTM features 1 l Ultra low power consumption: 85mW at 20Msps (using external references).
l Adjustable consumption versus speed.
APPLICATIONS
s s s s s s High-end infra-red imaging X-Ray medical imaging High-end CCD cameras Scanners and digital copiers Test instrumentation Wireless communication
s s s s s s
Single supply voltage: 2.5V Digital I/O supply voltage: 2.5V/3.3V compatible -90.5dBc SFDR and 73.1dBc SNR at Fin=10MHz when using external references (VINpp=2.5V) Differential analog input-driving Built-in reference voltage with external bias capabilities Digital output high impedance mode
ORDER CODES
Part Number TSA1401IF TSA1401IFT EVAL1401/AB Temperature Range -40C to +85C -40C to +85C Package TQFP48 TQFP48 Evaluation board Conditioning Tray Tape & Reel Marking SA1401 SA1401
1) OPTIMWATT(TM) is a ST deposited trademark for products features allowing optimization of power efficiency at chip/application level.
PIN CONNECTIONS (top view)
D0 (LSB)
DESCRIPTION
GNDBE
The TSA1401 is a 14-bit, 20MHz sampling frequency Analog to Digital Converter using deep submicron CMOS technology combining high performances with very low power consumption.The TSA1401 is based on a pipeline structure with digital error correction to provide excellent static linearity and dynamic performances. Typically designed for multi-channel applications and high-end imaging equipment, where low consumption is a must, the TSA1401 only dissipates 85mW at 20Msps when using external references, 110mW using internal references. Its power consumption adapts relative to sampling frequency. Differential signals are applied on the inputs for optimum performance. The TSA1401 reaches an SFDR of -90.5dBc and an SNR of 73.1dBc at Fin=10MHz when increasing the input dynamic range to 2.5V by using the voltage reference, TS431 (1.24V). A tri-state capability is available on the output buffers, enabling a Chip Select.The TSA1401 is available in the industrial temperature range of 40C to +85C and in a small 48-lead TQFP package.
December 2003
VCCBE
VCCBI
AGND
AVCC
AVCC
DFSB
OEB
SRC
NC
index corner
48 47 46 45 44 43 42 41 40 39 38 37 36 D1 35 D2 34 D3 33 D4
IPOL 1 VREFP 2 VREFM 3 AGND 4 VIN 5 AGND 6 VINB 7 AGND 8 INCM 9 AGND 10 AVCC 11 AVCC 12 13 14 15 16 17 18 19 20 21 22 23 24 DVCC DGND NC DGND DVCC DGND CLK GNDBE VCCBE GNDBI OR D13(MSB)
DR
TSA1401
32 D5 31 D6 30 D7 29 D8 28 D9 27 D10 26 D11 25 D12
PACKAGE
7 x 7 mm TQFP48
1/19 1/19
TSA1401 1 ABSOLUTE MAXIMUM RATINGS
Symbol
AVCC, DVCC, VCCBI VCCBE VIN, VINB, VREFP, VREFM, VINCM IDout Tstg ESD
ABSOLUTE MAXIMUM RATINGS
Parameter
Analog, digital, digital buffer Supply voltage 1 Digital buffer Supply voltage 1 Analog inputs Digital output current Storage temperature Electrical Static Discharge - HBM: Human Body Model2 - CDM-JEDEC Standard
Values
-0.3V to 3.3V 0V to 3.6V -0.3V to AVCC+0.3V -100mA to 100mA +150 2000 700 A
Unit
V V V mA C V
Latch-up
Class3
1) All voltage values, except differential voltage, are with respect to network ground terminal. The magnitude of input and output voltages must not exceed -0.3V or VCC 2) ElectroStatic Discharge pulse (ESD pulse) simulating a human body discharge of 100 pF through 1.5k 3) ST Microelectronics Corporate procedure number 0018695
OPERATING CONDITIONS Symbol
AVCC DVCC VCCBI VCCBE
Parameter
Analog Supply voltage Digital Supply voltage Digital buffer Supply voltage Digital buffer Supply voltage
Test conditions
Min
2.25 2.25 2.25 2.25
Typ
2.5 2.5 2.5 2.5
Max
2.7 2.7 2.7 3.3
Unit
V V V V
BLOCK DIAGRAM
+2.5V VREFP REFMODE
GNDA VIN INCM VINB stage 1 stage 2 stage n Reference circuit IPOL VREFM
Sequencer-phase shifting CLK
DFSB OEB
Timing
Digital data correction DR DO TO D13 OR GND
Buffers
2/19
ABSOLUTE MAXIMUM RATINGS
PIN DESCRIPTIONS Pin Name I/O
IPOL VREFP VREFM AGND VIN VINB INCM AVCC DVCC DGND CLK NC GNDBI GNDBE VCCBE OR D13(MSB)D0(LSB) DR VCCBI REFMODE OEB DFSB I
TSA1401
No
1
Pin Description
Analog bias current input - adjusts polarization current versus Fs. Top Reference Voltage - may be used as a voltage generator output or used as an I/O 2 input to adjust the input dynamic range (VIN-VINB=2x(VREFP-VREFM)). I 3 Bottom Reference Voltage. Usually connected to GND (see AN p12 for details) I 4, 6, 8, 10, 48 Analog ground. I 5 Positive Analog input. I 7 Negative Analog Input. Internal Common Mode - may be used as a voltage generator output for input sigI/O 9 nal common mode or used as an input to force the internal common mode (see AN p12 for more details). I 11, 12, 46, 47 Analog Power Supply (2.5V). I 13, 14 Digital Power Supply (2.5V) (Clock). I 15, 17,19 Digital Ground (Clock). I 16 CMOS Clock Input. NA 18, 42 Non Connected Pin. I 20 Digital Ground (Internal Buffer). I 21,40 Digital Ground (External Buffer). I 22, 39 Digital Power Supply (External Buffer, 2.5V/3.3V). O 23 Over Range Indicator, if D0-D13='1' or `0', OR='1'. Data CMOS Outputs (2.5V/3.3V). O 24-37 O I I I I 38 41 43 44 45 Data Ready Signal (2.5V/3.3V). Digital Power Supply (Internal Buffers 2.5V). REFMODE='VIL', internal references active. REFMODE=`VIH', external references must be applied. Output Enable Input. If OEB='VIH' then D0-D13 in `High Z' state. Data Format Select Input - If DFSB='VIH' then D13 is standard binary output coding; if DFSB='VIL' then D13 is two's complemented.
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TSA1401 2 ELECTRICAL CHARACTERISTICS
ELECTRICAL CHARACTERISTICS
AVCC = DVCC = VCCBI =VCCBE = 2.5V, Fs= 20MHz, Fin= 10MHz, VIN-VINB@ -1.0dBFS, VREFM= 0V, VREFP=1V, INCM=0.5V (external references), Tamb = 25C (unless otherwise specified)
Timing Characteristics
Symbol
FS DC TC1 TC2 Tod Tpd Ton Toff
Parameter
Sampling Frequency Clock Duty Cycle Clock pulse width (high) Clock pulse width (low)
Test conditions
Min
0.5
Typ
Max
20
Unit
MHz % ns ns
50 25 25 6 7.5 8.5 1 1 11
Data Output Delay (Fall of Clock 10pF load capacitance to Data Valid) Data Pipeline delay Falling edge of OEB to digital output valid data Rising edge of OEB to digital output tri-state
ns cycles ns ns
Timing Diagram
N+4 N+3 N+5 N+6
N+2 N-1 N N+1
N+7 N+8
CLK
8.5 clk cycles OEB Tod Toff N-8 N-7 N-6 N-5 N-4 N-3 Ton N-1 N
DATA OUT
DR
HZ state
4/19
ELECTRICAL CHARACTERISTICS Dynamic Characteristics
Symbol
SFDR1
TSA1401
Parameter
Test conditions
Min
Typ
-89 -91.5 -91
Max
-74
Unit
Spurious Free Dynamic Range Fin=10MHz, VREFP=1V Fin=10MHz, VREFP=1.24V (TS431) Fin=10MHz, internal references
dBFS
SNR1
Signal to Noise Ratio
Fin=10MHz, VREFP=1V Fin=10MHz, VREFP=1.24V (TS431) Fin=10MHz, internal references
68
71.5 73.1 70 -85 -85.9 -86 -71 dBc dBc
THD1
Total Harmonic Distortion
Fin=10MHz, VREFP=1V Fin=10MHz, VREFP=1.24V (TS431) Fin=10MHz, internal references
SINAD1
Signal to Noise and Distortion Ratio
Fin=10MHz, VREFP=1V Fin=10MHz, VREFP=1.24V (TS431) Fin=10MHz, internal references
66
71 72.85 69.9 dBc
ENOB1
Effective Number of Bits
Fin=10MHz, VREFP=1V Fin=10MHz, VREFP=1.24V (TS431) Fin=10MHz, internal references
10.9
11.7 12 11.5 bits
1) Typical values have been measured using the evaluation board on a dedicated test bench.
Accuracy
Symbol
OE GE DNL INL Offset Error Gain Error Differential Non Linearity Integral Non Linearity Monotonicity and no missing codes
Parameter
Min
Typ
-3 0.04 0.8 2
Max
Unit
LSB % LSB LSB
Guaranteed
Analog Inputs
Symbol
VIN-VINB Cin Zin BW
Parameter
Analog Input Voltage, Differential Analog Input capacitance Analog Input impedance Analog Input Bandwidth (-3dB)
Test conditions
Min
Typ
2 4.0
Max
Unit Vpp pF k MHz
Fs=20MHz Full power, VIN-VINB=2.0Vpp, Fs=20MHz
3.3 1000
Internal Reference Voltage
Symbol
REFP REFM INCM
Parameter
Top internal reference voltage Bottom internal reference voltage Internal common mode voltage
Test conditions
Min
0.75
Typ
0.84 0
Max
0.9
Unit
V V
0.4
0.44
0.5
V 5/19
TSA1401
Symbol
RrefO
ELECTRICAL CHARACTERISTICS
Parameter Test conditions
REFMODE='0': int references
Min
Typ
18.7
Max
Unit
Reference output impedance
External Reference Voltage
Symbol
VREFP VREFM VINCM RrefI Vpol
Parameter
Forced Top reference voltage Bottom reference voltage Forced common mode voltage Reference input impedance Analog bias voltage
Test conditions
REFMODE='1'
Min
0.8 0 0.4
Typ
Max
1.3 0.2 1
Unit
V V V k
7.5 REFMODE='1' 1.22 1.27 1.34
V
Power Consumption
Symbol
ICCA ICCD ICCBI ICCBE ICCBEZ Pd
Parameter
Analog Supply current Digital Supply Current Digital Buffer Supply Current Digital Buffer Supply Current Digital Buffer Supply Current in High Impedance Mode
Test conditions
REFMODE='0' REFMODE='1'
Min
Typ
40 30 595 1 2.3 10 110 851 104 791 80
Max
37 700 1.5 6 150
Unit
mA A mA mA A mW
Power consumption in normal opera- REFMODE='0' tion mode REFMODE='1' Power consumption in High Impedance mode Thermal resistance (TQFP48) REFMODE='0' REFMODE='1'
110
PdZ
96
mW C/W
Rthja
1) Typical values have been measured using the evaluation board on a dedicated test bench.
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ELECTRICAL CHARACTERISTICS Digital Inputs and Outputs
Symbol Parameter Test conditions Clock inputs
VIL VIH IIL IIH Logic "0" voltage Logic "1" voltage Low input current High input current DVCC=2.5V 2.0 TBD TBD
TSA1401
Min
Typ
Max
Unit
0.8
V V A A
Digital inputs
VIL VIH IIL IIH Logic "0" voltage Logic "1" voltage Low input current High input current VCCBE=2.5V 0.75 VCCBE TBD TBD 0.25 VCCBE V V A A
Digital Outputs
VOL VOH Logic "0" voltage Logic "1" voltage VCCBE=2.5V, Iol=10A VCCBE=2.5V, Ioh=10A 2.45 0.1 V V
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TSA1401 3
DEFINITIONS OF SPECIFIED PARAMETERS
DEFINITIONS OF SPECIFIED PARAMETERS
Signal to Noise and Distortion Ratio (SINAD) Similar ratio as for SNR but including the harmonic distortion components in the noise figure (not DC signal). It is expressed in dB. From the SINAD, the Effective Number of Bits (ENOB) can easily be deduced using the formula: SINAD= 6.02 x ENOB + 1.76 dB. When the applied signal is not Full Scale (FS), but has an A0 amplitude, the SINAD expression becomes: SINAD= 6.02 x ENOB + 1.76 dB + 20 log (2A0/FS) The ENOB is expressed in bits. Analog Input Bandwidth The maximum analog input frequency at which the spectral response of a full power signal is reduced by 3dB. Higher values can be achieved with smaller input levels. Effective Resolution Bandwidth (ERB) The band of input signal frequencies that the ADC is intended to convert without loosing linearity i.e. the maximum analog input frequency at which the SINAD is decreased by 3dB or the ENOB by 1/2 bit. Pipeline delay Delay between the initial sample of the analog input and the availability of the corresponding digital data output, on the output bus. Also called data latency. It is expressed as a number of clock cycles.
3.1 Static Parameters
Static measurements are performed through the method of histograms on a 2MHz input signal, sampled at 20Msps, which is high enough to fully characterize the test frequency response. An input level of +1dBFS is used to saturate the signal. Differential Non Linearity (DNL) The average deviation of any output code width from the ideal code width of 1LSB. Integral Non linearity (INL) An ideal converter presents a transfer function as being the straight line from the starting code to the ending code. The INL is the deviation for each transition from this ideal curve.
3.2 Dynamic Parameters
Dynamic measurements are performed by spectral analysis, applied to an input sine wave of various frequencies and sampled at 20Msps. Spurious Free Dynamic Range (SFDR) The ratio between the amplitude of fundamental tone (signal power) and the power of the worst spurious signal (not always an harmonic) over the full Nyquist band. It is expressed in dBc. Total Harmonic Distortion (THD) The ratio of the rms sum of the first five harmonic distortion components to the rms value of the fundamental line. It is expressed in dB. Signal to Noise Ratio (SNR) The ratio of the rms value of the fundamental component to the rms sum of all other spectral components in the Nyquist band (Fs/2) excluding DC, fundamental and the first five harmonics. SNR is reported in dB.
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TYPICAL PERFORMANCE CHARACTERISTICS 4 TYPICAL PERFORMANCE CHARACTERISTICS
Fs=20MHz; Icca=40mA
80 12 11.9 77 11.8 11.7 74 71 68 65 0 5 10 15 20 Fin (Mhz) 25 30
ENOB
TSA1401
Fig. 1: Linearity vs. Fin, Internal References
Fig. 4: Linearity vs. Fin, External References (REFP=1V) Fs=20MHz; Icca=28mA
Dynamic parameters (dB) 80 77 74 71 68 65 5 10 15 20 25 30
SINAD SNR ENOB
12
Dynamic parameters (dB)
11.6 11.5 11.4 11.3
SINAD
11.6 11.4 11.2 11
SNR
11.2 11.1 11
Fin (Mhz)
Fig. 2: Distortion vs. Fin, Internal References
Fs=20MHz; Icca=40mA; Internal references
-70 -75
Fig. 5: Distortion vs. Fin, External References (RefP=1V) Fs=20MHz; Icca=28mA
-70
Distortion (dBc)
Distortion (dBc)
-75 -80 -85 -90
SFDR THD
-80
THD
-85
SFDR
-90 -95
-95 -100
-100 0 5 10 15 Fin (Mhz) 20 25 30
5
10
15 20 Fin (Mhz)
25
ENOB (Bits)
30
30
11.8
ENOB (Bits)
Fig. 3: 2nd. and 3rd. harmonic vs. Fin, Internal References, Fs=20MHz; Icca=40mA
-60 -65 -70
Fig. 6: 2nd. and 3rd. harmonic vs. Fin, External References (REFP=1V) Fs=20MHz;
Icca=28mA
-60 -65 -70
Distortion (dB)
-75 -80 -85 -90 -95 -100 -105 -110 0 5 10 15 Fin (Mhz) 20 25 30
H3 H2
Distortion (dB)
-75 -80 -85 -90
H 2 H 3
-95 -100 -105 -110 5 10 15 20 F (Mhz) in 25
9/19
TSA1401
TYPICAL PERFORMANCE CHARACTERISTICS
Fig. 7: SFDR vs. input amplitude (FS=2x0.86V)
Fs=20Msps; Fin=5Mhz;Icca=40mA,
-20 -30
SFDR(dBc and dBFS)
-40 -50 -60 -70 -80 -90
SFDR(dBFS) SFDR(dBc)
-100 -110 -30
-25
-20
-15 SFSR(dB)
-10
-5
0
Fig. 8: Single-tone 16K FFT at Fs=20 Msps, Internal references
Fin=5MHz, Icca=40mA,Vin@-1dBFS, SFDR=-89.3dBc, THD=-84.5dBc, SNR=70.5dB, SINAD=70.3dB, ENOB=11.5 bits
0 -2 0 -4 0 -6 0 -8 0 -1 0 0 -1 2 0 -1 4 0 -1 6 0 -1 8 0 0 5
F (M h z)
Fig. 9: Single-tone 16K FFT at Fs=20Msps, External References TS4041
Fin=5MHz, Icca=40mA, Vin@-1dBFS, VREFP=1.225V SFDR=-87.5dBc, THD=-85.4dBc, SNR=73.3dB, SINAD=73dB, ENOB=11.84 bits
20 0 -2 0
Power spectrum
-4 0 -6 0 -8 0 -1 0 0 -1 2 0 -1 4 0 -1 6 0
0 5 10
F (M h z)
10/19
TYPICAL PERFORMANCE CHARACTERISTICS
Static parameter: Differential Non Linearity Fs=20MSPS; Fin=1MHz; Icc=40mA;N=524288pts
1 .2 1 0 .8 0 .6 0 .4 0 .2 0 -0 . 2 -0 . 4 -0 . 6 -0 . 8
TSA1401
Static parameter: Integral Non Linearity Fs=20MSPS; Fin=1MHz; Icc=40mA; N=524288pts
2 .5 2 1 .5 1 0 .5 0 -0 . 5 -1 -1 . 5 -2 -2 . 5
11/19
TSA1401 5 APPLICATION INFORMATION
APPLICATION INFORMATION
The TSA1401 is a High Speed Analog to Digital converter based on a pipeline architecture and the latest deep sub micron CMOS process to achieve the best performances in terms of linearity and power consumption. The pipeline structure consists of 14 internal conversion stages in which the analog signal is fed and sequentially converted into digital data. Each of the 14 stages consists of an Analog to Digital converter, a Digital to Analog converter, a Sample and Hold and an amplifier (gain=2). A 1.5bit conversion resolution is achieved in each stage. Each resulting LSB-MSB couple is then time-shifted to recover from the delay caused by conversion. Digital data correction completes the processing by recovering from the redundancy of the (LSB-MSB) couple for each stage. The corrected data are outputted through the digital buffers. Signal input is sampled on the rising edge of the clock while digital outputs are delivered on the falling edge of the clock. The advantages of such a converter reside in the combination of pipeline architecture and the most advanced technologies. The highest dynamic performances are achieved while consumption remains at the lowest level.
Internal references, common mode: When REFMODE is set to VIL level, TSA1401 operates with its own reference voltage generated by its internal bandgap. VREFM pin is connected externally to the Analog Ground while VREFP is set to its internal voltage (0.86V). The full scale of the ADC when using internal references is 1.8Vpp (to reduce the full scale if desired, VREFM may be forced externally). In this case VREFP and INCM are low impedance outputs. INCM pin (voltage generator 0.46V) may be used to supply the common mode, CM of the analog input signal. External references, common mode: In applications requiring a different full scale magnitude, it is possible to force externally VREFP and INCM (REFM must be connected to analog ground or forced externally). REFMODE set to VIH level will put in standby mode the internal references. In this case, VREFP, INCM are high impedance inputs and have to be forced by external references. TSA1401 shows better performances when the full scale is increased by the use of external references (see Figure 10 and 11). Fig. 10: Linearity vs. VREFP
Fin=5MHz;Fs=20Mhz;Icca=26mA;INCM=0.45V
80 12.4 12.2
ENOB
5.1 Analog Input Configuration 5.1.1 Analog input level and references
Dynamic parameters (dB)
To maximize the TSA1401's high-resolution and speed, it is advisable to drive the analog input differentially. The full scale of TSA1401 is adjusted through the voltage value of VREFP and VREFM: VIN-VINB=2(VREFP-VREFM) The differential analog input signal always presents a common mode voltage, CM: CM=(VIN+VINB)/2 In order for the user to select the right full scale according to the application, a control pin, REFMODE, allows to switch from internal to external references.
77 74 71 68 65 0.8 0.9 1 1.1 1.2 REFP (V) 1.3 1.4
SNR SINAD
12 11.8 11.6 11.4 11.2 11
12/19
APPLICATION INFORMATION
Fig. 11: Distortion vs. VREFP
Fin=5MHz;Fs=20Mhz;Icca=26mA;INCM=0.46V
-70 -75
Dynamic parameters (dB)
80 77 74 71 68 65 3 5 7 9 11 13 Fs (Mhz) 15 17 19
ENOB
TSA1401
Fig. 13: Linearity vs. Fs at Fin=5MHz, using TS4041 Icca optimised; VREFP=1.225V;
VREFM=GND; INCM=0.65V,
12.1 12 11.9
SNR SINAD
Distortion (dBc)
-80 -85 -90 -95 -100 0.8 0.9 1 1.1 REFP (V) 1.2 1.3 1.4
SFDR THD
11.7 11.6 11.5 11.4 11.3 11.2 11.1 21
An external reference voltage device may be used for specific applications requiring even better linearity, accuracy or enhanced temperature behavior. Using the STMicroelectronics TS821, TS4041-1.2 or TS431 Voltage Reference devices leads to optimum performances when configured as shown in Figure 12. The full scale is increased to 2.5Vpp differential and SNR and SINAD are enhanced as shown in Figure 13 . Fig. 12: External reference setting
1k
330pF 10nF 4.7F
REFMODE AVCC VIN VREFP
Fig. 14: Distortion vs. Fs at Fin=5MHz, using TS4041 Icca optimised; VREFP=1.225V;
VREFM=GND; INCM=0.65V
-70 -75
Distortion (dBc)
-80 -85
THD
-90 -95 -100 3 5 7 9
SFDR
100
TS4041 TS821 external
11 13 Fs (Mhz)
15
17
19
TSA1401
VINB
VREFM
reference
The magnitude of the analog input common mode, CM should stay close to VREFP/2. Higher level will introduce more distortion.
In multi-channel applications, the high impedance input of the references permits to drive several ADCs with only one Voltage Reference device.
5.1.2 - Driving the analog input
The TSA1401 has been designed to be differentially driven for better noise immunity. Some measurements have been done with single-ended signals. It degrades a little bit the performances, with an SFDR of -75dBc and an ENOB of 11.2 bits at 20Msps, Fin at 10MHz. The switch-capacitor input structure of TSA1401, presents a high input impedance (3.3k at Fs=20MHz) but not constant in time (see equivalent input circuit Figure 15). Indeed at the end of each conversion, the charge update of the
13/19
ENOB (Bits)
11.8
21
TSA1401
APPLICATION INFORMATION
sampling capacitor will draw/inject a small current transient on the input signal. One method to mask this transient current is a low-pass RC filter as shown on Figures 16 and Figure 17. A larger capacitor value compared to the sampling capacitor (appoximately 2pF) mounted in parallel of the two analog inputs signals will absorb the transient glitches. Fig. 15: ADC input equivalent circuit
configuration. Both inputs VIN and VINB are centered around the common mode voltage CM, that can be forced through INCM or supplied externally (in this case the internal common mode of the TSA1401 may be left internal at 0.45V, different from the input common mode value). Fig. 17: AC-coupled differential input
50 AVcc common mode Zin =1/(2Cs.Fs)=3.3k (Fs=20MHz) VIN Cin=4pF INCM 50
10nF 100k 33pF 100k 10nF
VIN INCM
TSA1401
VINB
AGND
5.2 - Clock management
The converter performances are very dependant on clock input accuracy, in terms of aperture delay and jitter. The voltage error induced by the jitter of the clock is: Verror=SR.Tj, where Tj is the jitter of the clock (system clock and ADC) and, SR is the slew rate of the input signal: SR max=2.Fin.FS (FS full scale, Fin input signal frequency)
VIN
100pF
Single-ended signal with transformer: Using an RF transformer is a good means to achieve high performance.
Figures 16 describes the schematics. The input signal is fed to the primary of the transformer, while the secondary drives both ADC inputs.
Fig. 16: Differential input configuration with transformer
Analog source ADT1-1 1:1
50
TSA1401
VINB INCM
Verror should be less than an LSB to guarantee no missing codes. At the end we have: Verror=2.Fin.FS.Tj and Verror< FS/2n Tj 330pF
10nF
4.7F
The internal common mode voltage of the ADC (INCM) is connected to the center-tap of the secondary of the transformer in order to bias the input signal around this common voltage, internally set to 0.46V. The INCM is decoupled to maintain a low noise level on this node. AC coupled differential input:
Tj <1ps. Consequently to target the maximum performances of the TSA1401, the clock applied should have a jitter below 1ps. The clock power supplies must be separated from the ADC output ones to avoid digital noise modulation at the output. It is strongly advised not to switch off the clock when the circuit is active (power supply on).
Figure 17 represents the biasing of a differential input signal in AC-coupled differential input
14/19
APPLICATION INFORMATION 5.3 - Power consumption optimization
The internal architecture of the TSA1401 enables the optimization of the power consumption according to the sampling frequency of the application. For this purpose, a resistor (value Rpol) is placed between IPOL and the analog Ground pins. At 20MHz sampling frequency, the Rpol for optimized consumption is equal to 41k. Optimized power consumption of the circuit versus the sampling frequency are shown in two configurations (Figure 18):
l REFMODE=0 internal references l REFMODE=1 external references
TSA1401
When OEB is set to low level again, the data is then valid on the output with a very short Ton delay(1ns). The timing diagram page 4 summarizes this operating cycle. Out of Range (OR) This function is implemented on the output stage in order to set up an "Out of Range" flag whenever the digital data is over the full scale range. Typically, there is a detection of all the data being at '0' or all the data being at '1'. This ends up with an output signal OR which is in low level state (VOL) when the data stay within the range, or in high level state (VOH) when the data are out of the range. Data Ready (DR) The Data Ready output is an image of the clock being synchronized on the output data (D0 to D13). This is a very helpful signal that simplifies the synchronization of the measurement equipment or the controlling DSP. As digital output, DR goes in high impedance state when OEB is asserted to High level as described in the timing diagram page 4.
Fig. 18: Analog Current consumption vs. Fs According value of Rpol polarization resistances: internal references
45 40
Rpol
140 120
35 30 25 20 5 10 Fs (Mhz) 15 20
Ipol_extref
80 60 40 20 0
Rpol (ohm)
Ipol (mA)
Ipol_intref
100
5.5 - Layout precautions
To use the TSA1401 circuit in the best manner at high frequencies, some precautions have to be taken for power supplies: - The separation of the analog signal from the digital part and from the buffers power supply is essential to prevent noise from coupling onto the input signal. - Power supply bypass capacitors must be placed as close as possible to the IC pins in order to improve high frequency bypassing and reduce harmonic distortion. - Proper termination of all inputs and outputs is needed; with output termination resistors, the amplifier load will be only resistive and the stability of the amplifier will be improved. All leads must be wide and as short as possible especially for the analog input in order to decrease parasitic capacitance and inductance.
5.4 - Digital outputs
Data Format Select (DFSB) When set to low level (VIL), the digital input DFSB provides a two's complement digital output MSB. This can be of interest when performing some further signal processing. When set to high level (VIH), DFSB provides a standard binary output coding. Output Enable (OEB) When set to low level (VIL), all digital outputs remain active and are in low impedance state. When set to high level (VIH), all digital outputs buffers are in high impedance state. It results in lower consumption while the converter goes on sampling.
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TSA1401
- To keep the capacitive loading as low as possible at digital outputs, short lead lengths when routing are essential to minimize currents when the output changes. To minimize this output capacitance, buffers or latches close to the output pins can relax this constraint. It is also helpful to use 47 to 56 ohms series resistors at the ADC output pins, located as close to the ADC output pins as possible. - Choose component sizes as small as possible (SMD). EVAL1401 evaluation board The characterization of the board has been made with a fully ADC devoted test bench. The schematic of the evaluation board is shown on figure 19. The analog signal must be filtered to be very pure. The dataready signal is the acquisition clock of the logic analyzer. All characterization measurement has been made with an input amplitude of +0.2dB for static parameters and -0.5dB for dynamic parameters
APPLICATION INFORMATION
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5
4
3
2
1
2 2
1
C1 470nF SM/C_0603
1
SMB_TRANCHE J1 2 SMB AVDD C4 470nF SM/C_0603 + F1 FIXATION CARTE TROU FIXATION 3MM B1 CALE DE PLACEMENT CALE_MPG
D
C2 10nF SM/C_0603 + + DGND 1
2 2
C3 330pF SM/C_0603 1
1 1 1 2 1
C5 10nF SM/C_0603
C6 330pF SM/C_0603
C7 47F 16V CAPA/POL/5.08
C8 47F 16V CAPA/POL/5.08
SMB_TRANCHE J2 2 SMB DVDD C9 47F 16V CAPA/POL/5.08 C10 470nF SM/C_0603 C11 10nF SM/C_0603 C12 330pF SM/C_0603 1 1
1
AVDD
DVDD
AGND
D
1
C13 470nF SM/C_0603
1
SMB_TRANCHE J3 2 SMB VDDBUF VDDBUF C16 470nF SM/C_0603 + AGND F3 FIXATION CARTE TROU FIXATION 3MM REFM + F4 FIXATION CARTE TROU FIXATION 3MM B3 SMB_TRANCHE J6 2 SMB VCMO VCMO + N ODI inverseur 2 1 3 SW1 inverseur INCM + C33 47F 16V CAPA/POL/5.08 C34 470nF SM/C_0603 C35 10nF SM/C_0603 C36 330pF SM/C_0603 TP1 picot picot/1pts
1 1
C14 10nF SM/C_0603 + 1 B2 1 +
C15 330pF SM/C_0603
C17 10nF SM/C_0603
C18 330pF SM/C_0603
C19 47F 16V CAPA/POL/5.08
C20 47F 16V CAPA/POL/5.08
SMB_TRANCHE J4 2 SMB REFP REFP C21 47F 16V CAPA/POL/5.08 C22 470nF SM/C_0603 C23 10nF SM/C_0603 C24 330pF SM/C_0603 F2 FIXATION CARTE TROU FIXATION 3MM
GNDBUF
CALE DE PLACEMENT CALE_MPG
1
SMB_TRANCHE J5 2 SMB REFM C25 47F 16V CAPA/POL/5.08 C26 470nF SM/C_0603 C27 10nF SM/C_0603 C28 330pF SM/C_0603 1 1
2
AGND R1 100 SM/R_0603 PT1 PICOT/2pts 2 1 R2 100 SM/R_0603 PT2 PICOT/2pts 2 1 PT3 PICOT/2pts 2 1 SMB_TRANCHE J7 2 SMB INCM
1
APPLICATION INFORMATION
CALE DE PLACEMENT CALE_MPG
1
C29 47F 16V CAPA/POL/5.08
C30 470nF SM/C_0603
C31 10nF SM/C_0603
C32 330pF SM/C_0603
AVDD AGND 2 AVDD
C
GNDBUF
C
R3 100 SM/R_0603
AGND
PWD
1 SW2 3
AGND
VDDBUF
AVDD VCMO NO DI PWD
VDDBUF
R4 100 SM/R_0603 PT4 PICOT/2pts 2 1 PT5 PICOT/2pts 2 1 AGND R5 100 SM/R_0603
AGND
Fig. 19: TSA1401 Evaluation board schematic
TP2 picot picot/1pts
1
TP3 picot picot/1pts
1 1 1
48 47 46 45 44 43 42 41 40 39 38 37
R6 100 SM/R_0603 PT6 PICOT/2pts 2 1 PT7 PICOT/2pts 2 1 AGND
3
48 47 46 45 44 43 42 41 40 39 38 37
IPOL REFP REFM R8 100 SM/R_0603 PT8 PICOT/2pts 2 1 2
R7 100 SM/R_0603
GNDBUF
AGND
DGND
VINP R11 100 SM/R_0603 PT9 PICOT/2pts 2 1 PT10 PICOT/2pts 2 1
B
AGND
U1 TQFP48 TQFP48
2
1
50 ohms R9 50K R_VARIABLE
1
1
VINM
J8 SMA SMA_TRANCHE CLOCK
CLK R10 47 SM/R_0603 DGND J9 SMA SMA_TRANCHE VINP IPOL 2
1
B
INCM R13 100 SM/R_0603 R15 100 SM/R_0603 PT11 PICOT/2pts 2 1 R16 100 SM/R_0603 PT12 PICOT/2pts 2 1 R17 100 SM/R_0603 PT13 PICOT/2pts 2 1 PT14 PICOT/2pts 2 1 R19 100 SM/R_0603 R20 100 SM/R_0603 PT15 PICOT/2pts 2 1
AVDD
1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25
1 2 3 4 5 6 7 8 9 10 11 12
36 35 34 33 32 31 30 29 28 27 26 25
13 14 15 16 17 18 19 20 21 22 23 24
R12 1K SM/R_0603
50 ohms R14 47 SM/R_0603 C37 10nF SM/C_0603 AGND J10 SMA SMA_TRANCHE VINM 2
1
VINP
CLK
13 14 15 16 17 18 19 20 21 22 23 24
D VDD
VDDBUF
C38 0pF SM/C_0603
DGND
A
GNDBUF
R18 47 SM/R_0603 50 ohms
VINM
A
AGND Willy Beule STMicroelectronics Crolles Title CVT_TQFP48_MB_V1
GNDBUF
Size B Date:
3 2
Document Number 1 Tuesday, October 08, 2002 Sheet
1
Rev A 1 of 1
5
4
TSA1401
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TSA1401
Printed circuit board - List of components
R e fe re n c e B 1 ,B 2 ,B 3 C 1 ,C 4 ,C 1 0 ,C 1 3 ,C 1 6 ,C 2 2 , C 2 6 ,C 3 0 ,C 3 4 C 2 ,C 5 ,C 1 1 ,C 1 4 ,C 1 7 ,C 2 3 , C 2 7 ,C 3 1 ,C 3 5 ,C 3 7 C 3 ,C 6 ,C 1 2 ,C 1 5 ,C 1 8 ,C 2 4 , C 2 8 ,C 3 2 ,C 3 6 C 7 ,C 8 ,C 9 ,C 1 9 ,C 2 0 ,C 2 1 ,C 2 5 , C 2 9 ,C 3 3 C38 J 1 ,J 2 ,J 3 ,J 4 ,J 5 ,J 6 ,J 7 J 8 ,J 9 ,J 1 0 P T 1 ,P T 2 ,P T 3 ,P T 4 ,P T 5 ,P T 6 , P T 7 ,P T 8 ,P T 9 ,P T 1 0 ,P T 1 1 , P T 1 2 ,P T 1 3 ,P T 1 4 ,P T 1 5 R 1 ,R 2 ,R 3 ,R 4 ,R 5 ,R 6 ,R 7 ,R 8 , R 1 1 ,R 1 3 ,R 1 5 ,R 1 6 ,R 1 7 ,R 1 9 , R20 R9 R 1 0 ,R 1 4 ,R 1 8 R12 S W 1 ,S W 2 T P 1 ,T P 2 ,T P 3 P a rt C ALE D E P LA C EM EN T 470nF 10nF 330pF 100 F 16V 0pF SMB SMA p ic o t
APPLICATION INFORMATION
P C B F o o tp r in t CALE_M PG S M /C _ 0 6 0 3 S M /C _ 0 6 0 3 S M /C _ 0 6 0 3 C A P A /P O L /5 .0 8 S M /C _ 0 6 0 3 SM B_TRANCHE SM A_TRANCHE P IC O T /2 p ts
100
S M /R _ 0 6 0 3
200K 4 9 .9 1K m ic ro s w itc h 1 p ic o t
R _ V A R IA B L E S M /R _ 0 6 0 3 S M /R _ 0 6 0 3 in v e rs e u r p ic o t/1 p ts
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PACKAGE MECHANICAL DATA 6 PACKAGE MECHANICAL DATA
TQFP48 MECHANICAL DATA
mm. DIM. MIN. A A1 A2 B C D D1 D3 e E E1 E3 L L1 K 0 0.45 0.05 1.35 0.17 0.09 9.00 7.00 5.50 0.50 9.00 7.00 5.50 0.60 1.00 3.5 7 0 0.75 0.018 1.40 0.22 TYP MAX. 1.6 0.15 1.45 0.27 0.20 0.002 0.053 0.007 0.0035 0.354 0.276 0.216 0.020 0.354 0.276 0.216 0.024 0.039 3.5 7 0.030 0.055 0.009 MIN. TYP. MAX. 0.063 0.006 0.057 0.011 0.0079 inch
TSA1401
0110596/C
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners. (c) 2003 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Repubic - Finland - France - Germany Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain Sweden - Switzerland - United Kingdom - United States http://www.st.com
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